The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a recess gate in a semiconductor device.
With the increase of integration density of semiconductor devices, it is difficult for a typical forming method of a planar gate to sufficiently secure refresh characteristics of the device, because junction leakage is caused by the increase of electric field as a gate channel length decreases and an implant doping concentration increases.
To solve the above limitation, a recess gate forming process is performed in such a way that an active region is patterned to form a recess therein and a conductive material is then filled into the recess to thereby form a recess gate. This recess gate process makes it possible to increase the gate channel length and decrease the implant doping concentration so that the refresh characteristics of the device can be enhanced accordingly.
FIGS. 1A and 1B illustrate cross-sectional views of a recess pattern of a semiconductor device according to the typical method. FIGS. 1C and 1D illustrate scanning electron microscope (SEM) micrographs of a horn occurring in the typical semiconductor device. Here, FIG. 1A is a sectional view taken along a major axis direction of an active region, and FIG. 1B is a sectional view taken along a minor axis direction of the active-region.
Referring to FIGS. 1A and 1B, an isolation structure 12 is formed in a substrate 11 to define an active region. A recess pattern 13 is formed using a recess mask and etch processes. The isolation structure 12 is formed through a typical shallow trench isolation (STI) process. A trench for device isolation is formed in a certain region of the substrate 11 such that the trench has an inclined sidewall of which a tilt angle (α) is 85° or smaller (refer to FIGS. 1B and 1C), for securing a gap-fill property of a device isolation insulating structure which will be formed in a following process. In addition, in order to secure an effective field oxide height (EFH), the isolation structure 12 is formed such that a top surface of the isolation structure 12 is higher than a top surface of the substrate 11 (see FIG. 1D).
Meanwhile, the recess pattern 13 has a V-shaped profile. Resultantly, due to the tilt angle (α) of the isolation structure 12, the EFH, and the V-shaped profile of the recess pattern 13, a horn H occurs at a portion where the recess pattern 13 and the isolation structure 12 are in contact with each other. Such a horn H causes a characteristic of a gate insulating layer to be degraded, and the horn H serves as a weak point vulnerable to stress. Moreover, the horn acts as a leakage current source, which leads to a lower yield.